VHDL Language Overview

VHDL, which stands for VHSIC (Very High Speed Integrated Circuit) Hardware Description Language, was developed in the early 1980s as a spin-off of a high-speed integrated circuit research project funded by the U.S. Department of Defense.
VHDL is designed to fill a number of needs in the design process. Firstly, it allows description of the structure of a design, that is how it is decomposed into sub-designs, and the connection between the sub-designs.
Secondly it allows the specification of the design function using programming language forms. Thirdly, it allows a design to be simulated before being manufactured. In 1987, VHDL has been adopted as a standard by the IEEE (IEEE STD 1076-1987).
The standard was revised in 1993 (IEEE STD 1076-1993) to include a number of significant improvements.

Consistent statement declarations
Direct instantiation of entities and configurations
Extended identifiers, allowing any printable character in a name
Opening, closing and appending to files
New predefined attributes
New shift, rotate and xnor operators
A value of type std_logic_vector can be written as a string with an explicit number base
Constants and constant expressions may be associated with input ports in the port map Declarations within a generate statement
Postponed processes which execute in the last delta of the simulation time
Pure (default) and impure functions
Shared variables, variables that may be accessed by more than one process
The keyword unaffected, which indicates a condition when a signal is not given a new assignment in a conditional signal assignment
The group construct to group a collection of VHDL objects
Labels on sequential statements
Report statement for writing messages

This reference guide contains information about most items that are available in the VHDL language. All subjects contain one or more examples and link(s) to other subjects that are related to the current subject.
This reference guide is not intended to replace the IEEE Standard VHDL Language Reference Manual, IEEE STD 1076-1993. The VHDL syntax description in this reference manual uses the following grammar:

Syntax enclosed in square brackets [ ] is optional.
The VHDL comment syntax, two adjacent hyphens --, has the same meaning.
light Turquoise words are keywords in the VHDL language.
Underlined syntax belongs to the VHDL'93 language, but not to the VHDL'87.

VHDL Language Overview

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