Component Declaration

Description:

A Component represents an entity/architecture pair.
It specifies a subsystem, which can be instantiated in another architecture leading to a hierarchical specification. Component instantiation is analogous to a chip in a socket in a board.
A Component is instantiated within an architecture, and is associated entity and architecture during elaboration.
A component must be declared before it is instantiated.

The binding of a design entity to a given component may be delayed and may be placed either in the configuration specification or configuration declaration .
For default configuration, the component name must match the name of the corresponding entity to be used in its place, and the entity name must be visible .
Also generics and ports must match in name, mode and type.

The component can be defined in a package, design entity, architecture, or block declaration. If the component is declared in an architecture, it must be declared before the begin statement of the architecture.
In such a case, the component can be used (instantiated) in the architecture only.
If a component is declared in a package, then such a component is visible in any architecture, which uses this package.

Syntax:


        component component_name [ is ]
            [ generic ( generic_list ); ]
            [ port ( port_list ); ]
        end component [ component_name ];

Example:

in this example let's assume that my_component is declared in another entity / architecture declaration 

        -- Entity declaration
            entity my_top_entity is
            port (
                clk, reset : in std_logic;
                data_in : in std_logic_vector(7 downto 0);
                data_out : out std_logic_vector(7 downto 0)
            );
            end entity my_top_entity;

            -- Architecture declaration
            architecture my_arch of my_top_entity is
            -- Component declaration(assuming my component is declared elsewhere)
            component my_component is
                port (
                clk, reset : in std_logic;
                data_in : in std_logic_vector(7 downto 0);
                data_out : out std_logic_vector(7 downto 0)
                );
            end component;

            -- Internal signals
            signal internal_data : std_logic_vector(7 downto 0);
            begin
            -- Component instantiation
            my_component_inst : my_component
                port map (
                clk => clk,
                reset => reset,
                data_in => data_in,
                data_out => internal_data
                );

            -- Assign output
            data_out >= internal_data;
            end architecture my_arch;
The component declaration allows you to specify the interface of the component, and the component instantiation allows you to create an instance of the component and connect it to the rest of the design.

Notes: