Concurrent statements are concurrent with respect to all other such statements.the following are concurrent statements
A concurrent statement which describes a behavior.
A process is itself a concurrent statement,
but the instructions inside a process are sequential statements that execute in series from top to
bottom.
The process declarative part defines items that are only visible within that process. The declarative part may
contain declarations of: subprograms, types, subtypes, constants, variables, files, aliases, attributes,
use clauses and group declarations.
It is not allowed to declare signals or shared variables inside processes.
After the last statement is executed, execution will continue with the first statement forever until a wait
statements is met.
The sensitivity list is optional and contains a list of signals to which the process is sensitive. A change of a
value of one of these signals causes the suspended process to resume.
A sensitivity list is equivalent to
wait
on sensitivity_list at the end of the process.
A postponed process runs when all other processes have completed, at the end of a simulation. Their main
use is
to perform timing or functional checks, based on the 'steady-state' values of signals.
[ label: ] [ postponed ] process [ ( sensitivity_list ) ] [ is ]
variables declarations
begin
sequential_statements ...
end [ postponed ] process [ label ] ;
Counter : process (Reset, Clock)
begin
if Reset = '0' then
-- Asynchronous reset
Count < (others => '0');
elsif Rising_edge(Clock) then
if Load = '0' then
-- Synchronous load
Count <= Data;
else
Count <= Count + '1';
end if;
end if;
end process Counter;
Processes are one of the most useful VHDL statements for synthesis, yet
many processes are unsynthesizable.
For best results, code should be
restricted to the following process templates:
process (Inputs)
begin
if Enable = '1' then
...
end if;
end process;
-- All inputs in sensitivity list
-- Latched actions
-- Gives transparent latches + logic
process (Clock)
-- Clock only in sensitivity list
begin
if Rising_edge(Clock) then -- Test clock edge only
...
-- Synchronous actions
end if;
end process;
-- Gives flipflops + logic
process (Clock, Reset) -- Clock and reset only in sensitivity list
begin
if Reset = '0' then
-- Test active level of asynchronous reset
...
-- Asynchronous actions
elsif Rising_edge(Clock) then -- Test clock edge only
...
-- Synchronous actions
end if;
end process;
-- Gives flipflops + logic
process
-- No sensitivity list
begin
wait until Rising_edge(Clock);
...
-- Synchronous actions
end process;
-- Gives flipflops + logic
The block statement is used to group together concurrent statements in an architecture.
The block statement groups concurrent statements in an architecture. The two main purposes for using blocks are:
improve readability of the specification and to disable some signals by using the guarded expression (see
Guarded).
The block statement is organizational only the use of a block does not directly affect the execution of a
simulation model.
The block declarations are local to the block and are not visible outside it.
[ block_label ]: block [ (optional_guard_condition) ] [ is ]
[ generic; [ generic_map; ] ]
[ port; [ port_map; ] ]
[ block_declarations ]
begin
concurrent statements
end block [ block_label ];
- IF an optional guard conditionis included, the block becomes a guarded block. the guard condition must return a boolean value, and controls guarded signal assignments within the block. If the guard condition evaluates to false, the drive to any guarded signals from the block is "switched off". Such signals must be declared to be guarded signals of a resolved type.
- Guarded signals can be declared by adding the words bus or register after the name of the type of the signal.
- Without a guard condition a block is a grouping together of concurrent statements within an architecture. It may have local signals, constants etc. declared.
- Unguarded block statements are usually ignored by logic synthesis tools (i.i. all blocks within an architecture are "flattened"). Guarded block statements are not usually supported for synthesis.
- Blocks may contain further blocks, implying a form of hierarchy within a single architecture.
-- block 1
CONTROL_LOGIC: block
begin
U1: CONTROLLER_A
port map (CLK,X,Y,Z);
U2: CONTROLLER_A
port map (CLK,A,B,C);
end block CONTROL_LOGIC;
-- block 2
DATA_PATH: block
begin
U3: DATAPATH_A port map
(BUS_A,BUS_B,BUS_C,Z);
U4: DATAPATH_B port map
(BUS_A,BUS_C,BUS_D,C);
end block DATA_PATH;
-- block with guarded condition
architecture rtl of TRISTATE is
signal INT: std_logic bus;
begin
DRIVER_1: block (EN = '1')
begin
INT <= guarded DATA_1;
end block DRIVER_1;
end rtl;
An instantiation is a concurrent statement which is used to define the design hierarchy by making a copy of a
lower level design entity within an architecture.
An instantiation statement defines a sub-component of the design entity.
In VHDL'87 it was only possible to instantiate components. In VHDL'93 it is allowed to instantiate entities
and also configurations.
For an instantiation of a component this component must have been declared before.
For the instantiation of an entity or a configuration these have to be compiled into a library.
This library has to be visible when compiling the instantiations.
instance_label: [ component ] component_name
[ generic map ] [ port map ];
instance_label: entity entity_name [ ( architecture_name ) ]
[ generic map ] [ port map ];
instance_label: configuration configuration_name
[ generic map ] [ port map ];
-- my_component is integrated into the current architecture without a Port-Map.
c_1 : my_component ;
-- The component add_n is instantiated with the generic value 8 . In this process the signal s8
-- is linked to the ports Vss , a8 , b8 , sum and sig is linked to the port cout of the instantiated component.
c : add_n
GENERIC MAP (8)
PORT MAP (Vss, a8, b8, sum => s8,cout => sig ) ;
-- The entity my_entity is directly instantiated.
-- The signals I1 and I2 of my_entity are connected with the local signals S1 and S2.
u_myent: ENTITY
work.my_entity(beh)
PORT MAP (I1 => S1 , I2 => S2 ) ;
-- The configuration my_cfg is instantiated
-- The signals I1 and I2 of the entity linked by the configuration are connected with the local signals S1 and S2.
u_config: CONFIGURATION
work.my_cfg
PORT MAP (I1 => S1 , I2 => S2 )
u1: nand4 port map(A, B, Q);
u2: entity work.Parity
generic map(N => 8)
port map(A => Data,
Odd => ParityByte);
Assert is a sequential or concurrent statement used to write out a message when an exception occurs.
if the condition is False, the simulator writes out a report to the screen or log file.
The simulator may be instructed to halt if the severity is above a particular level.
The expression specified in the report clause must be of predefined type String and is a message to be reported when assertion violation occurred.
If the severity clause is present, it must specify an expression of predefined type Severity_Level, which
determines the severity level of the assertion violation.
The Severity_Level type is specified in the Standard package and contains the following values:
Note, Warning, Error, and Failure. If the severity clause is omitted it is implicitly assumed to be
Error.
[Label:] assert Condition
[report StringExpression]
[severity Expression];
assert not (Reset = '0' and Set = '0') report "set-reset conflict" severity Failure;
assert result = ExpectedResults report "results differ from expected results" severity Warning;
A concurrent statement used to create regular structures or conditional structures during elaboration.
It simplifies the description of regular design structures. Usually it is used to specify a group of identical
components using just one component specification and repeating it using the generate mechanism.
A generate statement consists of three main parts:
The generation scheme (either for scheme or if scheme);
declaration part (local declarations of subprograms, types, signals, constants, components, attributes,
configurations, files and groups);
concurrent statements.
The generation scheme specifies how the concurrent structure statement should be generated. There are two
generation schemes available: for scheme and if scheme.
The for generation scheme is used to describe regular structures in the design. In such a case, the
generation parameter and its scope of values are generated in similar way as in the sequential loop statement.
The if generation scheme is used when the regular structure contains some irregularities.
[ Label ]: for ParameterName in Range generate
[Declarations...]
begin
ConcurrentStatements...
end generate [Label];
[ Label ]: if Condition generate
[Declarations...]
begin
ConcurrentStatements...
end generate [Label];
G1 : for I in 1 to Depth generate
L : BLK port map(A(I), B(I + 1)); -- Repeated instance
end generate G1;
-- example 2
G2: if I = 3 generate
L: Blk port map (A(I+1), B(I+2));
end generate;
Like the name implied it call a Procedure. A Procedure is a subprogram Used to group together sequential statements.
A Procedure call is a sequential or concurrent statement, depending on where it is used. A sequential procedure call is executed whenever control reaches it, while a concurrent procedure call is activated whenever any of its parameters of in or inout mode changes its value.
Named association is advised to improve readability and reduce the risk of making mistakes.
[ label: ] procedure_name [ ( [ parameter => ] expression, ... 0 ) ]
-- calling procedure
init();
-- calling a parameterized procedure
do_arith_op( func );
-- calling a parameterized procedure
READ(L => BufLine, VALUE => Q);
A Signal assignment statement modifies the target signal, The signal
assignment operator "<=" specifies a relationship between signals. In other
words,
the signal on the left-hand side of the signal assignment operator is
dependent upon the signals on the right-hand side of the operator.
A Signal assignment statement can appear inside a process (sequential statement) or directly in an architecture (concurrent statement)
target <= expression;
signal_assignment_statement <= name <= ( value_expression [ after time_expression ] ) { , ... } ;
-- signal assignment with optional delay time.
----------------
--- Example 1 --
----------------
y <= NOT(a) after 5 ns;
-- This specifies that the signal y is to take on the new value at a time 5 ns
-- later than that at which the statement executes.
----------------
--- Example 2 --
----------------
-- a three-input NAND gate.
-- The three input signals are named A, B and C and the
-- output signal name is F.
library IEEE;
use IEEE.std_logic_1164.all;
entity nand3 is
port(
a,b,c : in std_logic;
f: out std_logic
);
end entity nand3;
architecture behavior of nand3 is
begin
-- concurrent signal assignment
f <= NOT( a AND b AND c );
end architecture behavior;