A configuration is a construct that defines how the design hierarchy is linked together.
It allows you to define the relationship between the different components of your design, such as entities,
architectures, and libraries.
A simple configuration contains reference to only one architecture body. Hierarchical
configurations allow to
nest configurations. This mechanism allows binding component instantiations with the design entities
down the
hierarchy.
When the ports and generics in the component declaration are not equal to their counterparts in the entity
declaration.
One can use an explicit notification on how the ports and generics in the entity should be
bound to
ports and generics of the component instance. The generic map and port map are used for this purpose.
configuration configuration_name of entity_name is
[ configuration_declarations ]
for architecture_name
[ "configuration_item" ] -- construct defined below
end for;
end [ configuration ] [ configuration_name ];
"configuration_item" = for instance_label : component_name
[ "use_item" ]
[ generic_map ] -- construct defined below
[ port_map ];
[ configuration_item ]
end for;
"use_item" = entity [ library_name. ] entity_name [ (architecture_name) ] |
configuration [ library_name. ] configuration_name ;
The structure of a VHDL configuration file typically consists of the following elements:
configuration <configuration_name> of <entity_name> is
This line starts the configuration declaration and specifies the entity for which the configuration is being defined.
for <architecture_name>
This line specifies the architecture of the entity that the configuration is targeting.
for <component_name> : <component_entity_name> use entity <library_name>.<entity_name>(<architecture_name>);
This section defines the binding between a component instance and the entity and architecture that it should use.
end <configuration_name>;
This line marks the end of the configuration declaration.
Here's an example of a VHDL configuration file:
configuration my_config of my_entity is
for my_arch
for comp1 : my_component
use entity work.my_component_entity(my_component_arch);
end for;
for comp2 : another_component
use entity lib2.another_component_entity(another_component_arch);
end for
end for;
end my_config;
In this example:
my_component_arch, which is located in
the work library.The configuration file is used to specify how the different design units (entities, architectures, and
components) are connected within the overall design.
This allows you to easily change the interconnections
between components without modifying the individual design units.
-- MUX component
entity Mux is
port (
sel : in std_logic;
a, b : in std_logic;
y : out std_logic
);
end entity Mux;
-- MUX architecture 1
architecture arch1 of Mux is
begin
y <= a when sel = '0' else b;
end architecture arch1;
-- MUX architecture 2
architecture arch2 of Mux is
begin
process(sel, a, b)
begin
if sel = '0' then
y <= a;
else
y <= b;
end if;
end process;
end architecture arch2;
Now, let's create a top-level entity that uses the MUX component:
entity TopEntity is
port (
sel : in std_logic;
a, b : in std_logic;
y : out std_logic
);
end entity TopEntity;
architecture top_arch of TopEntity is
component Mux is
port (
sel : in std_logic;
a, b : in std_logic;
y : out std_logic
);
end component;
begin
mux_inst : Mux
port map (
sel =< sel,
a =< a,
b =< b,
y =< y
);
end architecture top_arch;
Finally, let's create a configuration file to bind the MUX component to the appropriate architecture:
configuration mux_config of TopEntity is
for top_arch
for mux_inst : Mux
use entity work.Mux(arch2);
end for;
end for;
end configuration mux_config;