Data Objects

An data object is a named item that can be used to represent and store data. Each data object has a specific data type and a unique set of possible values.
Constant declaration can be used in Entity, Package, Process, Architecture, Procedure, Function
These values depend on the definition of the data type used for that object. There are four different data objects.

• Constant
• Variable
• Signal
• Shared Variable

Constant

Definition:

A constant is an object whose value cannot be changed once defined for the design. Constants may be explicitly declared or they may be sub-elements of explicitly declared constants, or interface constants.
Constants declared in packages may also be deferred constants.

Syntax:

        constant constant_name : data_type := [ value , expression ];
        

Description:

A constant is used to give a name to a value, this makes it easier to read and maintain the code. The data type in the constant declaration can be of scalar or composite type and it can be constrained.
A constant cannot be of the file or access type.
If a constant is an array or a record then none of its elements can be of the file or access type. The visibility of constants depends on the place of their declaration. The constants defined in the package can be used by several design units.
The constant declaration in the design entity is seen by all the statements of the architecture bodies of this entity.
The constants defined in the declaration part of the design unit is seen in all bodies related to this design, including the process statement.
The constant defined in the process can only be used in this process.

Example:

          constant bytes : integer := 8;
          constant PI : real := 3.141592;
          constant PERIOD : time := 10 ns;
     

The values of array constants of types other than string, bit_vector and std_logic_vector, must be set using aggregates.

Example 2:

        type T_CLOCK_TIME is ARRAY(3 downto 0) of integer range 0 to 9;
        constant TWELVE_O_CLOCK : T_CLOCK_TIME := (1,2,0,0);
     

In a package, a constant may be deferred. This means its value is defined in the package body. the value may be changed by re-analysing only the package body.

Example 3:

          package E is
          -- A deferred constant declaration
            constant exp : real ;
        end E;

        package body E is
            constant exp : real := 2.71 ;
        end E;
     

Provided with the correct type, constants may be used in any expression. They may be associated with generics of component instances and passed into procedures.

        process
        type T_DATA is array (0 to 3)
              of bit_vector(7 downto 0);
        constant DATA : T_DATA :=
                  ("00001000",
                   "00010001",
                   "00100010",
                   "01000011");
      begin
        for I in DATA'range loop
          serialize_byte(DATA(I),DOUT);
        end loop;
      end process;
   

Notes

• Constants are supported for synthesis, provided with type acceptable to the logic synthesis tool.
• They are either synthesized as connections to logic '1' or '0', or are used to help minimise the number of gates required.
• Deferred constants may not bwe supported.
• Use constants to define data parameters and lookup tables, which may substitute function calls. The simulation time of such lookups is significantly shorter than that of function calls.

Variable

Definition:

A variable stores a value. Variable declaration can be used in Process, Procedure, Function

Syntax:

        variable variable_name : data_type [ := expression ];
    

Description:

A variable is an object that stores information local to a process, architecture or subprogram (procedures and functions) in which it is defined. A variable's values can be changed during simulation through the variable assignment statements.
A variable declaration includes one or more identifiers, a (sub)type indication and an optional initial value for the variable. A variable can be declared to be of any type or subtype available, either constrained or unconstrained.
Variables that are declared in processes are initialized with their default values at the start of the simulation. Variables declared in subprograms are initialized each time the subprogram is called.
The scope of variables is limited to the process or subprogram they are defined in.
The only exception to this rule is a shared variable, which may be shared by multiple processes.

Example:

        variable X: integer := 5;
        variable running : boolean := false ;
        variable Y,Z: integer ;
        variable sum, average, largest : real;
        variable start, finish : time := 0 ns;
     

Variables within subprograms (functions and procedures) are initialized each time the subprogram is called:

        function PARITY ( input : std_logic_vector) return std_logic is
            variable tmp : std_logic := '0';
            begin
                for j in input'range loop
                    tmp := tmp xor input(j)
                end loop;
                -- no need to initialize tmp
                return tmp ;
            end PARITY;
     

Variables in processes, except for "FOR LOOP" variables, receive their initial values at the start of the simulation time (time = 0 ns)

        process (A)
        variable tmp : std_logic := '0';
     begin
        tmp := '0';
        -- in this example we need to reset
        -- tmp to '0' each time the process
        -- is activated
        for I in A'low to A'high loop
           TMP := TMP xor A(I);
        end loop;
        ODD <= TMP;
     end process;
     

Notes

• A Variable may be given an explicit initial value when it is declared. If a variable is not given an explicit value, it's default value will be the leftmost value ('left) of its declared type.
• Unlike signals, variables have neither history nor future, because according to its definition, each variable has only current value. No checking for the last event, time elapsed since the last event, previous value, etc. can be performed on variables.
• If a value of a variable is read before it is assigned in a clocked process then a register will be synthesized for this variable. A similar situation inside a combinatorial process may lead to generation of a latch.
• In a "clocked process", each variable which has its value read before it has had an assignment to it will be synthesized as the output of a register.
• In a "combination process", reading a variable before it has had an assignment may cause a latch to be synthesized.

Signal

Definition:

Signal is an object with a past history of values. A signal may have multiple drivers, each with a current value and projected future values. The term signal refers to objects declared by signal declarations and port declarations.

Syntax:

        -- signal declaration
        signal signal_name : data_type ;
        -- signal assignment
        signal_name <= expression;

        -- signal declaration and assignment
        signal signal_name : data_type := expression ;

    

Description:

A signal represents an electrical connection, wire or bus. Signals are used for communication between processes. Signals can be explicitly declared in the declarative part of:

• A signal may never be of a file or access type.
• package declaration: signals declared in a package are visible in all design entities using the package (through the use clause).
• architecture: such signals are visible inside the architecture only.
• block: the scope of such signals is limited to the block itself.
• subprogram (function and procedure): the scope of such signals it limited to the subprogram itself.

A port declaration in an entity is an implicit signal declaration. A signal declared this way is visible in all architectures assigned to that entity. A signal can get a default value in its declaration. If the signal declaration does not contain a default value,
then the default value of the signal is the left bound of the specified type. The default value is ignored for synthesis; use an explicit reset to get both the VHDL and the synthesized hardware into the same known state.
A signal declared with a kind statement can have individual drivers disconnected from the resolution function. This signal must be of a resolved type.
A register type signal with no drivers connected retains its previous value.
The bus type signal relies on the resolution function to supply a "no-drive" value. Most synthesis tools ignore resolution functions.

Example:

        -- signal declarations
        signal a,b : std_logic ;
        signal clk : time ;
        -- signal assignment
        a <= '0';
        b <= '1';
        -- signals are only updated after a wait for statement
        wait for 5 ns;

        -- signal declaration and assignment
        signal S3: std_logic := '0';
        signal counter : natural range 0 to 500000 := 0;   -- half period

     

Notes

• Signals are declared between the architecture <architecture_name> of <entity_name> is line and the begin statements in the VHDL file. This is called the declarative part of the architecture.
• signal assignment uses the <= operator.
• Value of Signals are only updated when a process is paused after a <wait for ?ns> statement

Shared Variable

Definition:

A shared variable is used to share information between processes.

Syntax:

        shared variable variable_name : data_type ;
    

Description:

Shared variables can be used to share information between processes. They may be declared within an architecture, block, generate statement, or package. Shared variables may be accessed by more than one process.
However, the language does not define what happens if two or more processes make conflicting accesses to a shared variable at the same time. shared variables should be used with caution

Example:

        library IEEE;
        use IEEE.std_logic_1164.all;

        -- package declaration
        package my_package is
            shared variable my_shared_var : integer := 0;
        end my_package;

        -- entity declaration
        entity my_entity is
            Port ( clk : in std_logic);
        end my_entity;

        architecture behavioral of my_entity is
            use work.my_package.all;
        begin
            process(clk)
            begin
                if rising_edge(clk) then
                    my_shared_var := my_shared_var + 1; -- Shared Variable assignment
                end if;
            end process;

            -- Another process that reads the shared variable
            process
            begin
                wait until rising_edge(clk):
                report "Shared variable value: " & integer'image(my_shared_var);
            end process;

        end behavioral;
     

Notes

• shared variables can lead to issues with concurrent access and race condition, so be caution.
• Signals are better choice for connecting concurrent processes together.