Identifiers

Identifiers is either a name or a reserved word.

Name

• Basic identifiers
  • - Must begin with a letter.
  • - Begins and ends with the character ‘\’.
  • - The \ character may be included in the identifier, but must then be doubled, e.g.: \ab\\cd\
  • May include an unlimited amount of all graphical characters and in any order.
  • Are case-sensitive.
• Extended identifier
  • - MAY contain letter and digits.
  • - May contain letters and digits.
  • - May contain the character ‘_’, but not as first or last character and not more than one in a row.
  • identifiers Are not case-sensitive.

Syntax:

        identifier             -- simple name
        "operator"              -- "+","-","*"
        attribute_name
        name.name. ...         -- selected name
        name(range)            -- slice name
        name(expression, ...)  -- indexed name
    

Description:

Any declaration that introduces a named item defines an identifier which enables reference to such an item by using this identifier. However, it is not always possible to refer to an item or part of it by using just its identifier.
general form of reference to items is by a name. Names can also indicate objects of the access type, elements of the composite type, parts of the composite object or unit attributes which have an identifier in their declaration.
The name can have any of the following forms:

• simple name-- The simple name consists only of the identifier, which is assigned to a given unit in its declaration
• operator symbol -- The operator symbol is a string literal, which indicates the function declared for such an operator symbol
• attribute name -- The combination of the identifier and its attribute
• selected name -- A selected name is commonly used to pick an item out of a library or package
• indexed name -- An indexed name is used to pick an individual item out of an array

Example:

       ABC_66 -- simple name
       "+"    -- operator
       Clk'Event -- attribute name
       IEEE.std_logic_1164."nor" --selected name
       SignalSlice(12 to 15) -- slice name
       sign(5) -- indexed name
    

Notes

• None of the VHDL reserved words may be used as a name for other items.

Alias

Syntax:

       alias alias_name : data_type is name ... ;
    

Description:

The alias declares an alternative name for any existing object:signal, variable, constant or file. It can also be used for "non-objects": virtually everything, which was previously declared, except for labels, loop parameters, and generate parameters. If an alias denotes a subprogram (including an operator) or enumeration literal then a signature (matching the parameter and result type) is required.

• simple name-- The simple name consists only of the identifier, which is assigned to a given unit in its declaration
• operator symbol -- The operator symbol is a string literal, which indicates the function declared for such an operator symbol
• attribute name -- The combination of the identifier and its attribute
• selected name -- A selected name is commonly used to pick an item out of a library or package
• indexed name -- An indexed name is used to pick an individual item out of an array

A name consists of letters, digits and underscores. The extended_identifier has to be used when the first character is not a letter, the last character is an underscore, or when the identifier has two adjacent underscores.

Example:

        signal Instruction: std_logic_vector(15 downto 0);

        alias OpCode   : std_logic_vector(3 downto 0) is Instruction(15 downto 12);
        alias SrcAddr  : std_logic_vector(1 downto 0) is Instruction(11 downto 10);
        alias DestAddr : std_logic_vector(1 downto 0) is Instruction(9 downto 8);
        alias InstData : std_logic_vector(7 downto 0) is Instruction(7 downto 0);
    

Notes

• Many synthesis tools do not support aliases.

Group

Syntax:

        group group_template_name is( class, ... );              -- group template declaration
        class = entity | architecture | label | signal | function | group | type | {etc.}  [ < > ] 
        group group_name: group_template_name ( name, ... );   -- group declaration
    

Description:

Groups relate different named items for the purposes not specified by the language, and have no meaning for simulation. Groups can be used to pass information to downstream tools. Setting up a group requires two declarations (a group template declaration and a group declaration).
The group template declaration defines pattern of a group connecting named items with the specified class. A class with range <> allows zero or more units belonging to this group, and must be the last item in this class list.
The group declaration connects named items having the specified characteristics. The user-defined attributes are connected individually with each named item, so each separate named item can have its own attributes.
In case when the user wants to assign information to several related named items, a group consisting of these units can be defined, and then specify attributes for the entire group.
The attribute specification of a group is realized in a similar way to other attribute specifications. First, the attribute of a given type is declared and it is specified for the given group in its declaration part which contains declaration of the particular group.

Example:

    architecture Rtl of Ent1 is
    group Operations is (function, label <>);
    group Counters: Operations ("+", C1, C2);
    begin
    C1: X <= A + B;
    C2: Y <= C + D;
    end Rtl;
            

Notes

• Groups can be nested