Basic Modeling

Description:

Every VHDL design description consists of at least one entity & architecture pair.
We can put many entity & architecture pair and connect then together to form a complete circuit.
The identifier in an entity & architecture names the module so that it can be referred to later.

Entity

Description:

An Entity declaration describes the circuit as it appears from the outside world, its input and output interfaces (ports and generics).
In a schematic design, you might think of an entity declaration as being analogous to a block symbol on a schematic.
An Entity declaration provides the complete interface for a circuit. You have all information you need to connect that circuit into other, higher-level circuits.
The Entity declaration may be preceded by the library and use clauses.
This way all declarations defined in a package will be visible for the entity and all architectures assigned to it. An Entity is used in combination with an architecture.
Together they describe the behaviouror structure of an hierarchical block of hardware (a design entity). The architecture can be assigned to one entity only but one entity may be assigned to multiple architectures.
The Entity declares the design name. In addition, it defines generics which provide static information (like timing parameters or bus width) to a design, and ports which provide communication channels between the design and its environment.

Syntax:

        entity identifier is
            [ generic ( generic_list ); ]
            [ port ( port_interface_list) ; ]
            [ begin ]
            [ concurrent statements  | passive-procedure-call |
            passive-process-statement  ]
        end [ entity ] [ identifier ] ;

        -- the port interface syntax
        -- interface_list ⇐ ( identifier : [ mode ] type , ...)
        -- mode ⇐ in , out , inout
        
    

Example 1:

This example describes an entity named adder, with two input ports and two output ports, all of type bit.We can list the ports in any order; we do not have to put inputs before outputs.
We can also have bidirectional ports, with mode inout, to model devices that alternately sense and drive data through a pin.

        entity Adder is
        port ( a, b : in bit;
                sum,carry : out bit );
        end entity adder;
        
    

Example 2:

in this example assuming that word in define in TYPES we have two inputs ports mode in and one output port mode out. and a passive procedure call

        library IEEE, TYPES;
        use IEEE.STD_LOGIC_1164.all;
        use TYPES.TypePackage.all;

        entity Design is
	        generic (n : NATURAL);
	        port (
		        data : in std_logic_vector(n downto 0);
		        clk : in std_logic;
		    outData : out word);
        begin
	        PeriodCheck(clk, MaxPeriod); -- Passive procedure call
        end entity Design;
        
    

Example 3:

        library ieee;
        use ieee.std_logic_1164.all;

        entity BCD_Decoder is
        generic (Size: integer := 4);
        port (BCD: in std_logic_vector(2 downto 0);
                Enable: in std_logic;
                LED: out std_ulogic_vector (Size-1 downto 0));
        constant Zero: std_ulogic_vector(Size-1 downto 0) := (others => '0');
        begin
        assert (BCD /= "111") report "BCD is 7" severity note;
        end BCD_Decoder;
        
    

Notes:

• An entity is the interface of a design.
• Each entity in a design must have a unique name while each entity can have several architectures. Everything declared in an entity is automatically accessible in its architectures.
• It is possible to write an entity without any generics, ports and statements. In fact this is used in constructing testbenches.
• Note the order of the declarations in the declaration part of the entity.
• The purpose of the statement part is to be able to verify the behavior of the signals declared in the declaration part, i.e. the ports.

Architecture

Description:

The internal operation of a module is described by an architecture body.
An architecture body generally applies some operations to values on input ports, generating values to be assigned to output ports.
The operations can be described either by processes, which contain sequential statements operating on values, or by a collection of components representing sub-circuits.
Where the operation requires generation of intermediate values, these can be described using signals, analogous to the internal wires of a module.

Syntax:

        architecture identifier of entity-name is
		 { subprogram-declaration | subprogram-body | type-declaration |
			 subtype-declaration | constant-declaration | signal-declaration |
			 shared-variable-declaration | file-declaration | alias-declaration |
			 component-declaration | attribute-declaration | attribute-specification |
			 configuration-specification | disconnect-specification | use-clause |
			 group-template-declaration | group-declaration }
        begin
		 { concurrent-statement }
        end [ architecture ] [ architecture-name-identifier ];
        
    

Example:

        architecture behaviour of Adder is
        begin
            sum <= a xor b;
            carry < a and b;
        end architecture behaviour;
        
    

Notes:

• An architecture may not be used without an entity.
• All declarations defined in an entity are fully visible and accessible within each architecture assigned to this entity.