Package

Description:

A VHDL package is simply a way of grouping a collection of related declarations that serve a common purpose. They allow us to separate the external view of the items they declare from the implementation of those items.
The external view is specified in a package declaration, whereas the implementation is defined in a separate package body.
Packages are stored in libraries. A package is split into a package declaration (mandatory) and a package body (optional).
The purpose of a package is to declare shareable types, subtypes, constants, signals, files, aliases, component, attributes and groups.
Once a package is defined, it can be used in multiple independent designs. Items declared in a package declaration are visible in other design units if the use clause is applied.

Syntax:

        package identifier is
	        { package_declarative_item }
        end [ package ] [ identifier ];
        
    

The identifier provides a name for the package, which we can use elsewhere in a model to refer to the package.
Inside the package declaration we write a collection of declarations, including type, subtype, constant, signal and subprogram declarations.
These are the declarations that are provided to the users of the package.

Example 1 :

        library IEEE;
        use IEEE.std_logic_1164.all;

        package cpu_types is
            constant word_size : POSITIVE := 16;
            constant address_size : POSITIVE := 24;
            subtype word is bit_vector(word_size - 1 downto 0);
            subtype address is bit_vector(address_size - 1 downto 0);
            type status_value is (halted, idle, fetch, mem_read, mem_write,
            io_read, io_write, int_ack);
        end package cpu_types;
        
    

Example 2 :

        library IEEE;
        use IEEE.std_logic_1164.all;

        package Utils is
	        constant Size : POSITIVE;
	        subtype Vec8 is STD_LOGIC_VECTOR(7 downto 0);
	        function Parity (V : Vec8) return STD_LOGIC;
        end Utils;
        
    

Notes:

• A package declaration may contain a subprogram (function or procedure) declaration; the subprogram body is not allowed here and must appear in the package body
• A package body must accompany a package declaration if the declaration contains subprogram declarations or deferred constants.
• Only definitions placed in the package declaration are visible outside the package.

Package Body

Description:

A package body defines the bodies of subprograms and the values of deferred constants defined in the package.
The package body includes complete definitions of subprogram body declarations as well as values of deferred constants declared in the corresponding package declarations.
Other declarations (similar to those of package declaration) are also allowed here, but are visible only inside the package body.
The deferred constant, which has been declared in a package declaration, may be used before its full declaration only in a default expression for a local generic parameter, local port or formal parameter of subprogram.

Syntax:

        package body package_name is
            package_body_declarations
        end [ package body ] [ package_name ];
        
    

Example:

        package body Utils is
        constant Size: positive := 16;
        function Parity (V: Vec8) return std_logic is
            variable B: std_logic := '0';
        begin
            for I in V'Range loop
            B:= B xor V(I);
            end loop;
            return B;
        end Parity;
        end Utils;
        
    

Notes:

• Declarations other than values of deferred constants and subprogram bodies are not visible outside the package body.
• Each package can have only one body.

Library Clause

Description:

VHDL library is a container that stores entities, architectures , and packages. The Library contains all the piece of code that is used frequently and can be shared with other designs.
A VHDL library is usually implemented as a directory in the host file system. The library name is mapped to the pathname of that directory by the VHDL tool.
There are two predefined libraries, which are used implicitly in every design: Std and Work. The Std library contains the packages Standard and Textio.
The Work library is a working library, where all user-created and analyzed design units are stored.
Also user-specified packages are stored in the working library Work.

Syntax:

        library IEEE;
        library Work, IpCores;
        
    

Notes:

• A library specified in a library clause of the primary design unit (entity, configuration or package) is visible in each secondary unit (architecture or package body) associated to it.
• Library Std need not to be specified. Both library packages are automatically included in every design unit.

Use Clauses

Description:

The use clause makes names defined in a library directly visible within another region of the VHDL code.
The use clause is typically written at the top of an entity or at the top of a configuration (giving access to the entities and architectures in a library). The item_name specified in the use clause, specifies the item that will be visible.
If a designer wants to have all declarations in a package visible, then the item_name should be substituted by the reserved word all.
The use clause is valid for the design unit immediately following it and for all secondary design units assigned to this design unit (if it is a primary design unit).
If a file contains more than one design unit, then each design unit must have its own use clauses. In other words, use clauses are not global within a file.

Example:

        use IEEE.std_logic_1164.all;
        use WORK.ArithOp.Add;
        use WORK.all