Port

Description:

A Port declaration represents the interface of the circuit.
A port represents a pin or a related group of pins on a hardware component.
A port is, technically, a signal.

• in input port. This port can only be read. It is not allowed to assign a value to it.
• out output port. This port can only be assigned. It is not allowed to read from it.
• inout bi-directional port. Both assignments to such a port and reading from it are allowed.
• buffer output port with read capability. It differs from inout in that it can be updated by at most one source, whereas inout can be updated by zero or more sources.
• linkage The value of the port may be read or updated, but only by appearing as an actual corresponding to an interface object of mode linkage.

Syntax:

        port ( port_name, ... : [ mode ] data_type [ := Expression ] );

        mode = in | out | inout | buffer | linkage
        
    

Example:

        port (Clk, Rst: in std_logic;
            D: in std_logic_vector(3 downto 0);
            Status: out std_logic;
            Q: buffer std_logic_vector(3 downto 0);
        )
        
    

Port Map

Description:

A port map maps signals in an architecture to ports on an instance within that architecture.
Port maps can also appear in a block or in a configuration.
The connections can be listed via positional association or via named association. Within an instance, the port names are ports on the component or entity being instanced,
the expressions are signals visible in the architecture containing the instance. Within a configuration, the port names are ports on the entity, the expressions are ports on the component.
The elements of an array port can be connected individually when using named association.
Ports may be left unconnected using the keyword open.

Syntax:

        port map ( [ port_name => ] expression, ... )
        
    

Example:

    architecture Structure of Top is
        component CompA
            generic (...);
            port (
                Clk, Rst : in STD_LOGIC;
                D : in STD_LOGIC_VECTOR(3 downto 0);
                Rd : out STD_LOGIC;
                Q : out STD_LOGIC_VECTOR(3 downto 0));
        end component;
        begin
            u1 : CompA generic map(...)
            port map(Clock, Reset, DIn, QOut);
            u2 : CompA generic map(...)
            -- port map declaration
            port map(
                Clk => Clock,
                Rst => Reset,
                D => DIn,
                Rd => open,
                Q(0) => QOut1,
                Q(3 downto 1) => QOut2);
    end Structure;
        
    

Notes:

• Port declarations are signal declarations and port signals need not to be re-declared.
• A conversion function in a port map must have one parameter only.