VHDL Keywords

abs	access	after
alias	all	and
architecture	array	assert
attribute	begin	block
body	buffer	bus
case	component	configuration
constant	context	cover
disconnect	downto	else
elsif	end	entity
exit	file	for
function	generate	generic
group	guarded	if
impure	in	inertial
inout	is	label
library	linkage	literal
loop	map	mod
nand	new	next
nor	null	of
on	open	or
others	out	package
port	postponed	procedure
process	pure	range
record	register	reject
rem	report	return
rol	ror	select
severity	signal	shared
sla	sll	sla
srl	subtype	then
to	transport	type
unaffected	units	until
use	variable	wait
when	while	with
xnor	xor