Types

A set of values a set of operations.

Syntax:

            type type_name is array [ is data_type ];
    

Description:

All signals, variables, constants (i.e. objects) and expressions have a type. The type defines the set of values that the object or expression can have.
A type also determines the set of operations which can be performed on an object or expression. There are four classes of types in VHDL:

• scalar types: represent a single numeric value, or in the case of enumerated types, an enumeration value.
• composite types: represent a collection of values.
• access types: provide access to objects of a given type.
• files: provide access to objects that contain a sequence of values of a given type (typically disk files).

Apart from predefined types (available through the packages Standard, Std_logic_1164 and Numeric_std), the user can define his own types.
A user-defined type can be of any of the four classes mentioned above.
A value of one type cannot be assigned to an object of a different type. If a translation from one type to another is required, then type conversion must be applied.

Example:

        type State is (TReset, TWait, THold, THalt);
    

Notes

• VHDL is a strongly typed language which causes that two types defined in exactly the same way (i.e. lexically identical) but differing only by names will be considered different.
• The initial value of an object is the leftmost value of the type, i.e. the value on the left of the base enumeration.

Subtype

A value belongs to a subtype of a given type if it belongs to the type and satisfies the constraint; the given type is called the base type of the subtype.
A type is a subtype of itself. Such a subtype is said to be unconstrained because it corresponds to a condition that imposes no restriction.

Syntax:

            subtype subtype_name is base_type range range_constraint;
    

Description:

Subtype distinguishes a subset of values of some type.
The part of the subtype declaration is the subtype indication, which denotes some other type or subtype. The type_mark in a subtype_indication must refer to a type or a subtype that was declared earlier (Example 1).
The constraints given in the subtype indication must correspond to the subtype :

• scalar types - range constrains can be applied, for arrays - index constraints are applicable
• Records cannot have any constraints
• Access type may have index type constraints only when their type_mark denotes an array type
• If the subtype declaration does not contain any constraints then the subtype is the same as the (sub)type denoted by the type_mark.

A special form of the subtype indication may include a resolution function name (Example 2). This form is not allowed for declarations of access and file subtypes.
There are two predefined subtypes specified in the package STANDARD: natural and positive. Both are subtypes of the type INTEGER. The package std_logic_1164,
also contains declarations of subtypes, which are constrained subtypes of the std_logic: X01, X01Z, UX01, and UX01Z

Examples:

        subtype DIGITS is INTEGER range 0 to 9;
    

INTEGER is a predefined type and the subtype DIGITS will constrain the type to ten values only, reducing the size of registers if the specification is synthesized.

        type State is (TReset, TWait, THold, THalt);
        subtype Status is State;
    

        function RESOLVE_VALUE (anonymous: BIT_VECTOR) return BIT;
        subtype BIT_NEW is RESOLVE_VALUE BIT;
    

The subtype BIT_NEW is a resolved version of the type BIT due to the reference to a resolution function RESOLVE_VALUE specified earlier.

Notes

• A subtype declaration does not define a new type.
• A subtype is the same type as its base type; thus, no type conversion is needed when objects of a subtype and its base type are assigned (in either direction). Also, the set of operations allowed on operands of a subtype is the same as the set of operations on its base type.
• Using subtypes of enumerated and integer types for synthesis is strongly recommended as synthesis tools infer an appropriate number of bits in synthesized registers, depending on the range.