Instantiation

Description:

An instantiation is a concurrent statement defines a sub-component of the design entity.
It is used to define the design hierarchy by making a copy of a lower level design entity within an architecture.
The instantiation statement introduces a subsystem declared elsewhere.
In VHDL'93 , a direct instantiation of an entity bypasses the component and configuration.

• instantiation of a component
• instantiation of a design entity
• instantiation of a configuration

Instantiation of a component introduces a relationship to a unit defined earlier as a component (see Component).
The name of the instantiated component must match the name of the declared component.
The instantiated component is called with the actual parameters for generics and ports. The association list can be either positional or named.
It is not necessary to define a component to instantiate it the entity/architecture pair can be instantiated directly.
In such a direct instantiation, the instantiation statement contains the design entity name and optionally the name of the architecture to be used for this design entity.

Syntax:

        instance_label: [ component ] component_name
            [ generic map ] [ port map ];
        instance_label: entity entity_name [ ( architecture_name ) ]
            [ generic map ] [ port map ];
        instance_label: configuration configuration_name
            [ generic map ] [ port map ];
        
    

Example:

        -- component instantiation
        u1: Nand4 port map(A, B, Q);

        -- entity instantiation
        u2: entity Parity
            generic map(N =< 8)
            port map(A =< Data,
                Odd =< ParityByte);
        
    

Notes:

• An entity, architecture or configuration must be compiled into a library before the corresponding instance can be compiled.
  However, an instance of a component can be compiled before the corresponding design entity has even be written.